Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance

Abstract

We report for the first time experimental investigations on SOI, Si _1-x Ge _x OI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET I _ON by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si _1-x Ge _x OI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: I _ON x2700 for GeOI (compared to SOI).