Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
- 25 July 2008
- journal article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Design Automation of Electronic Systems
- Vol. 13 (3), 1-27
- https://doi.org/10.1145/1367045.1367049
Abstract
Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone. In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases . Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for. The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications.Keywords
This publication has 11 references indexed in Scilit:
- Software/Hardware Engineering with the Parallel Object-Oriented Specification LanguagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Multi-processor system design with ESPAMPublished by Association for Computing Machinery (ACM) ,2006
- SDF^3: SDF For FreePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Scenario-oriented design for single-chip heterogeneous multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
- Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphsPublished by Association for Computing Machinery (ACM) ,2006
- Global Analysis of Resource Arbitration for MPSoCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- An automated exploration framework for FPGA-based soft multiprocessor systemsPublished by Association for Computing Machinery (ACM) ,2005
- Multiprocessor mapping of process networksPublished by Association for Computing Machinery (ACM) ,2002
- Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chipPublished by Association for Computing Machinery (ACM) ,2001
- Static Scheduling of Synchronous Data Flow Programs for Digital Signal ProcessingInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1987