Describes a RISC (reduced-instruction-set computer) BiCMOS superscalar microprocessor containing 3.1 M transistors which executes up to three instructions per clock cycle. Clock frequency is 40 MHz with 8 mW dissipation. The chip includes a 32-b integer pipeline (IU), a memory management unit (MMU), a 20-kB instruction cache (I cache), a 16-kB data cache (D cache), an IEEE-compatible double-precision floating-point unit (FU), and a bus interface (BU). The chip supports built-in self-test, internal and JTAG boundary scan, in-circuit emulation for remote symbolic source-code debugging, and hardware to support multiprocessor system architecture. An on-chip phase-locked loop synchronizes external and internal clock edges. The chip is implemented in a 0.8- mu m triple-layer-metal salacided BiCMOS process. The die is 15.98*15.98 mm/sup 2/, with 166 active pins and 127 power/ground pins.<>