A 50MS/s (35mW) to 1ks/s (15μW) power scaleable 10b pipelined ADC with minimal bias current variation
- 30 August 2005
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
Abstract
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This publication has 2 references indexed in Scilit:
- CMOS low-power analog circuit designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low-power reconfigurable analog-to-digital converterIEEE Journal of Solid-State Circuits, 2001