Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process
- 1 July 2019
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We examined radiation hardness of a stacked transmission-gate flip flop and a stacked tristate-inverter flip flop, which are called STACKEDTGFF and STACKEDTIFF respectively. Stacked flip flops fabricated in FDSOI are stronger against soft errors than in bulk because all transistor channels are isolated by a BOX layer. We evaluated soft-error tolerance by neutron and heavy-ion irradiation. STACKEDTIFF is faster than STACKEDTGFF because of the difference of the number of gates along the data path. Those FFs did not flip by neutrons and the normal incidence of heavy ions with LET of less than 40 MeV-cm 2 mg. They are stronger against soft errors than a standard TGFF by two order of magnitude. We also investigated incident angle dependence of those FFs by heavy ions.Keywords
This publication has 15 references indexed in Scilit:
- Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMsIEEE Transactions on Nuclear Science, 2015
- A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOIIEEE Transactions on Nuclear Science, 2014
- Technology downscaling worsening radiation effects in bulk: SOI to the rescuePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- Terrestrial neutron-induced single-event burnout in SiC power diodesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- Theoretical Correlation of Broad Spectrum Neutron Sources for Accelerated Soft Error TestingIEEE Transactions on Nuclear Science, 2010
- Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant FluctuationIEEE Transactions on Electron Devices, 2010
- Model for Cumulative Solar Heavy Ion Energy and Linear Energy Transfer SpectraIEEE Transactions on Nuclear Science, 2007
- Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunityIEEE Transactions on Nuclear Science, 2005
- The impact of technology scaling on soft error rate performance and limits to the efficacy of error correctionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Upset hardened memory design for submicron CMOS technologyIEEE Transactions on Nuclear Science, 1996