Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
- 1 January 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 19 (9), 999-1010
- https://doi.org/10.1109/43.863640
Abstract
Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstationKeywords
This publication has 17 references indexed in Scilit:
- Optimal Wire-sizing Function With Fringing Capacitance ConsiderationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Minimum Crosstalk Switchbox RoutingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Minimum crosstalk channel routingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Gate sizing: a general purpose optimization approachPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Interconnect inductance effects on delay and crosstalk for long on-chip nets with fast input slew ratesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Generic global placement and floorplanningPublished by Association for Computing Machinery (ACM) ,1998
- Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationPublished by Association for Computing Machinery (ACM) ,1998
- High-level area and power estimation for VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948