On-chip decoupling capacitor optimization using architectural level prediction
- 10 December 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 10 (3), 319-326
- https://doi.org/10.1109/tvlsi.2002.1043335
Abstract
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.Keywords
This publication has 9 references indexed in Scilit:
- Vector Generation For Maximum Instantaneous Current Through Supply Lines For CMOS CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Decoupling capacitor calculations for CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis of ground bounce in deep sub-micron circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On-chip decoupling capacitor optimization for high-performance VLSI designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On-chip decoupling capacitor optimization using architectural level current signature predictionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Power distribution system design methodology and capacitor selection for modern CMOS technologyIEEE Transactions on Advanced Packaging, 1999
- Reducing power in high-performance microprocessorsPublished by Association for Computing Machinery (ACM) ,1998
- Interconnect and circuit modeling techniques for full-chip power supply noise analysisIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1998