A CMOS nested-chopper instrumentation amplifier with 100-nV offset
- 1 December 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (12), 1877-1883
- https://doi.org/10.1109/4.890300
Abstract
A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV//spl radic/Hz consuming a total supply current of 200 /spl mu/A.Keywords
This publication has 7 references indexed in Scilit:
- A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offsetIEEE Journal of Solid-State Circuits, 1999
- Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilizationProceedings of the IEEE, 1996
- A rail-to-rail ping-pong op-ampIEEE Journal of Solid-State Circuits, 1996
- An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiersIEEE Journal of Solid-State Circuits, 1994
- Concepts and focus point for intelligent sensor systemsSensors and Actuators A: Physical, 1994
- A CMOS chopper amplifierIEEE Journal of Solid-State Circuits, 1987
- A low-noise chopper-stabilized differential switched-capacitor filtering techniqueIEEE Journal of Solid-State Circuits, 1981