Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

28 September 2004

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 156-518 Vol.1
https://doi.org/10.1109/isscc.2004.1332641

Abstract

A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.

Keywords

VOLTAGE
POWER MEASUREMENT
MOS DEVICES
FREQUENCY MEASUREMENT
SEMICONDUCTOR DEVICE MEASUREMENT
CIRCUIT TESTING
LOGIC TESTING
ENERGY EFFICIENCY
DELAY
LOGIC DEVICES

This publication has 1 reference indexed in Scilit:

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
IEEE Journal of Solid-State Circuits, 2002

Cited by 40 articles