Disruptive prefetching
- 26 May 2015
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM)
Abstract
Caches are integral parts in modern computers; they leverage the memory access patterns of a program to mitigate the gap between the fast processors and slow memory components. Unfortunately, the behavior of caches can be exploited by attackers to infer the program's memory access patterns, by carrying out cache-based side-channel attacks, which can leak critical information. Secure caches that were proposed employ cache partitioning or randomized memory-to-cache mapping techniques to prevent these attacks. Such techniques may add to the complexity of cache designs. In this work, we suggest the use of specialized prefetching algorithms for the purpose of protecting from cache-based side-channel attacks. Our prefetchers can be combined with conventional set associative cache designs, are simple to employ, and require low incremental hardware overhead costs, if the base prefetching scheme is already employed. We integrated our prefetching policies with commonly used GHB and stride prefetching schemes, and compared their performance with the standard implementations of those schemes, on both conventional and secure cache designs. More specifically, our results show that the use of our secure prefetching policy delivers original prefetching performance when integrated with a stride prefetcher. Finally, we demonstrate how a disruptive prefetching scheme can protect the cache from an access based side-channel attack.Keywords
This publication has 16 references indexed in Scilit:
- Security Basics for Computer ArchitectsSynthesis Lectures on Computer Architecture, 2013
- Security testing of a secure cache designPublished by Association for Computing Machinery (ACM) ,2013
- DüppelPublished by Association for Computing Machinery (ACM) ,2013
- The gem5 simulatorACM SIGARCH Computer Architecture News, 2011
- New cache designs for thwarting software cache-based side channel attacksACM SIGARCH Computer Architecture News, 2007
- Cache-Collision Timing Attacks Against AESLecture Notes in Computer Science, 2006
- Cache Attacks and Countermeasures: The Case of AESLecture Notes in Computer Science, 2006
- Stride Directed Prefetching In Scalar ProcessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Data Cache Prefetching Using a Global History BufferPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Hitting the memory wallACM SIGARCH Computer Architecture News, 1995