An instruction throughput model of superscalar processors
- 24 January 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A framework for statistical modeling of superscalar processor performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Performance simulation toolsComputer, 2002
- Modeling architectural improvements in superscalar processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2000
- One billion transistors, one uniprocessor, one chipComputer, 1997
- Billion-Transistor ArchitecturesComputer, 1997
- The SimpleScalar tool set, version 2.0ACM SIGARCH Computer Architecture News, 1997
- The nonuniform distribution of instruction-level and machine parallelism and its effect on performanceIEEE Transactions on Computers, 1989