Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
- 1 January 2000
- book chapter
- conference paper
- Published by Springer Science and Business Media LLC in Lecture Notes in Computer Science
- p. 379-388
- https://doi.org/10.1007/3-540-44614-1_41
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Dynamic scheduling of tasks on partially reconfigurable FPGAsIEE Proceedings - Computers and Digital Techniques, 2000
- Run-time compaction of FPGA designsLecture Notes in Computer Science, 1997
- Programmable active memories: reconfigurable systems come of ageIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996
- Video communications using rapidly reconfigurable hardwareIEEE Transactions on Circuits and Systems for Video Technology, 1995