Challenges for the DRAM cell scaling to 40nm
- 6 April 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 4 pp.-339
- https://doi.org/10.1109/iedm.2005.1609344
Abstract
This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structuresKeywords
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