We present in this paper a detailed analysis of the electrical behaviour of NMOS transistors with gate lengths down to Lg = 30 nm where the source/drain extensions (SDE) were developed using ultra low energy implantation (As 1 keV) or plasma doping (PLAD) at low bias (1.5 kV). PLAD splits show excellent threshold characteristics in comparison with As 1 keV: delayed Vt roll-down, reduced short channel effect (SCE) and drain induced barrier lowering (DIBL). The Ion/Ioff trade-off analysis reveals a much lower Ioff for comparable gate lengths when using PLAD instead of ULE. These behaviours are explained by a reduced junction depth Xj, which is confirmed by a parameter extraction on transistor characteristics and by analytical modelling.