Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs
- 17 July 2014
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 61 (10), 2851-2861
- https://doi.org/10.1109/tcsi.2014.2333675
Abstract
Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as n-type or p-type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing VDD and GND by complementary input signals. Synthesis results of ISCAS'85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology.Keywords
This publication has 21 references indexed in Scilit:
- Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity TransistorsIEEE Transactions on Circuits and Systems II: Express Briefs, 2013
- Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich CircuitsPublished by EDAA ,2013
- The VTR projectPublished by Association for Computing Machinery (ACM) ,2012
- Reconfigurable Silicon Nanowire TransistorsNano Letters, 2011
- System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias IslandsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
- An Efficient Gate Library for Ambipolar CNTFET LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011
- Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 PrescalerIEEE Transactions on Circuits and Systems I: Regular Papers, 2009
- Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS applicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Enhanced Channel Modulation in Dual-Gated Silicon Nanowire TransistorsNano Letters, 2005
- Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakageIEEE Journal of Solid-State Circuits, 2002