Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
- 10 December 2010
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 31 (1), 90-98
- https://doi.org/10.1109/mm.2010.102
Abstract
To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance.Keywords
This publication has 6 references indexed in Scilit:
- The virtual write queuePublished by Association for Computing Machinery (ACM) ,2010
- Multifacet's general execution-driven multiprocessor simulator (GEMS) toolsetACM SIGARCH Computer Architecture News, 2005
- IBM power5 chip: a dual-core multithreaded processorIEEE Micro, 2004
- Eager writeback-a technique for improving bandwidth utilizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Memory access schedulingPublished by Association for Computing Machinery (ACM) ,2000
- Conflict-free access of vectors with power-of-two stridesPublished by Association for Computing Machinery (ACM) ,1992