The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
- 9 May 2003
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation - PLDI '03
- Vol. 38 (5), 38-48
- https://doi.org/10.1145/781131.781137
Abstract
No abstract availableKeywords
This publication has 25 references indexed in Scilit:
- Compile-time dynamic voltage scaling settingsPublished by Association for Computing Machinery (ACM) ,2003
- Critical power slopePublished by Association for Computing Machinery (ACM) ,2002
- Energy-conscious compilation based on voltage scalingPublished by Association for Computing Machinery (ACM) ,2002
- Control-theoretic dynamic frequency and voltage scaling for multimedia workloadsPublished by Association for Computing Machinery (ACM) ,2002
- Real-time dynamic voltage scaling for low-power embedded operating systemsPublished by Association for Computing Machinery (ACM) ,2001
- Power: a first-class architectural design constraintComputer, 2001
- The benefits of eventPublished by Association for Computing Machinery (ACM) ,2000
- The design and use of simplepowerPublished by Association for Computing Machinery (ACM) ,2000
- Design challenges of technology scalingIEEE Micro, 1999
- Energy dissipation in general purpose microprocessorsIEEE Journal of Solid-State Circuits, 1996