Disc-like copper vias fabricated in a silicon wafer: Design for reliability
- 1 May 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2008 58th Electronic Components and Technology Conference
- p. 1664-1666
- https://doi.org/10.1109/ectc.2008.4550201
Abstract
Simple formulas have been obtained for the evaluation of the 1) elastic stability of thin-and-large-diameter ("disc-like") copper vias fabricated in a silicon wafer and subjected, at elevated temperatures, to thermally induced compression, as well as of the level of the 2) cumulative stresses in an array of vias. Based on the computed data, we have concluded that, when the spacing between the vias in a via array is twice as large as the via diameter, the maximum cumulative tensile stress in the silicon wafer could be assessed by multiplying the "hoop" pressure due to a single via by the factor of 2.25.Keywords
This publication has 6 references indexed in Scilit:
- Copper Via Plating in Three Dimensional InterconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect TechnologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Through Wafer Copper Via for Silicon Based SiP ApplicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Mechanical effects of copper through-vias in a 3D die-stacked modulePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Applied Probability for Engineers and ScientistsJournal of Electronic Packaging, 1997
- Structural Analysis in Microelectronic and Fiber-Optic SystemsPublished by Springer Science and Business Media LLC ,1991