Understanding the trade-offs in multi-level cell ReRAM memory design
- 29 May 2013
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 50th Annual Design Automation Conference on - DAC '13
Abstract
Resistive Random Access Memory (ReRAM) is one of the most promising emerging memory technologies as a potential replacement for DRAM memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM.Keywords
This publication has 17 references indexed in Scilit:
- Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Metal–Oxide RRAMProceedings of the IEEE, 2012
- A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memoryApplied Physics Letters, 2012
- Multilevel resistive switching in Ti/CuxO/Pt memory devicesJournal of Applied Physics, 2010
- Investigation of State Stability of Low-Resistance State in Resistive MemoryIEEE Electron Device Letters, 2010
- Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti CapIEEE Electron Device Letters, 2009
- Architecting phase change memory as a scalable dram alternativePublished by Association for Computing Machinery (ACM) ,2009
- Multilevel resistive switching with ionic and metallic filamentsApplied Physics Letters, 2009
- High speed resistive switching in Pt∕TiO2∕TiN film for nonvolatile memory applicationApplied Physics Letters, 2007
- Derivation and implication of a novel DRAM bit cost modelIEEE Transactions on Semiconductor Manufacturing, 2002