Decimal addition in FPGA

1 April 2009

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 101-108
https://doi.org/10.1109/spl.2009.4914894

Abstract

This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.

Keywords

This publication has 2 references indexed in Scilit:

Synthesis of Arithmetic Circuits
Published by Wiley ,2005
The IBM z900 decimal arithmetic unit
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2001

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