A power-optimal repeater insertion methodology for global interconnects in nanometer designs
Top Cited Papers
- 16 December 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 49 (11), 2001-2007
- https://doi.org/10.1109/ted.2002.804706
Abstract
This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.Keywords
This publication has 13 references indexed in Scilit:
- On thermal effects in deep sub-micron VLSI interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A practical approach to DSM repeater insertion: satisfying delay constraints while minimizing area and powerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scalingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis of on-chip inductance effects for distributed RLC interconnectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
- Analysis and future trend of short-circuit powerIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
- Technology and design challenges for low power and high performancePublished by Association for Computing Machinery (ACM) ,1999
- A reduced clock-swing flip-flop (RCSFF) for 63% power reductionIEEE Journal of Solid-State Circuits, 1998
- An efficient technique for device and interconnect optimization in deep submicron designsPublished by Association for Computing Machinery (ACM) ,1998
- Sources of Power ConsumptionPublished by Springer Science and Business Media LLC ,1995
- FastCap: a multipole accelerated 3-D capacitance extraction programIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991