A secure Scan Design Methodology
- 1 January 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1 (15301591), 1-2
- https://doi.org/10.1109/date.2006.244019
Abstract
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presented in the literature in order to securize the scan chain. Nevertheless, the different proposed techniques are all ad hoc techniques, which are not always easy to integrate into a completely automated design flow or in an IP reuse environment. In this paper, we propose a scan chain integrity detection mechanism, which respects both automated design flow and IP reuse environmentKeywords
This publication has 1 reference indexed in Scilit:
- Scan based side channel attack on dedicated hardware implementations of Data Encryption StandardPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005