A Feasibility Study of Hybrid Dram and Flash Memory Management Unit

Abstract

In this research, we propose the flash memory aware memory management unit (MMU) that enables an efficient hybrid memory architecture. We design the proposed MMU based on the SSDAlloc hybrid memory architecture to make flash memory aware. Our challenge is to make flash memory suitable for hybrid memory architecture, which consists of DRAM and flash memory and works as main memory. The proposed MMU can reduce the overhead of the runtime library implementation, and improve the DRAM utilization efficiency. As a result, the proposed MMU can reduces more than half of page fault.