Optimization trade-offs for vector volume and test power
- 7 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A study of test quality/tester scan memory trade-offs using the SEMATECH test methods dataPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A survey of optimization techniques targeting low power VLSI circuitsPublished by Association for Computing Machinery (ACM) ,1995