Forced convective interlayer cooling in vertically integrated packages
- 1 May 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
- p. 1114-1125
- https://doi.org/10.1109/itherm.2008.4544386
Abstract
The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters les 200 mum. An experimental investigation with uniform and double-side heat flux at Reynolds numbers les 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mum and fluid structure heights of 100 to 200 mum were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 mum interconnect pitch to 2 at 4 cm2.Keywords
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