Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO $_2$ Charge Trapping Layer
- 8 January 2010
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nanotechnology
- Vol. 10 (2), 260-265
- https://doi.org/10.1109/tnano.2009.2038479
Abstract
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO2 charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si3N4 charge-trapping layer was also fabricated. Since HfO2 has a deeper conduction band than Si3N4, the device with the HfO2 charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si3N4 charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO2 charge-trapping layer to undergo more P/E cycles than that with the Si3 N4 charge-trapping layer.Keywords
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