An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS
Top Cited Papers
- 13 September 2016
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 51 (12), 2928-2940
- https://doi.org/10.1109/jssc.2016.2592623
Abstract
The successive-approximation-register (SAR) architecture is well known for its high power efficiency in medium-resolution analog-to-digital converters (ADCs). However, when considered for high-precision applications, SAR ADCs suffer from non-linearity resulting from capacitor mismatch and limited dynamic range due to comparator noise. This work presents a mismatch error shaping (MES) technique for oversampling SAR ADCs to achieve 105 dB in-band SFDR without calibration. The capacitor mismatch error is first-order high-pass filtered by simply delaying the reset of LSB capacitor array after sampling. The comparator thermal and flicker noise are also first-order shaped to high frequencies by noise shaping. The prototype in 55 nm CMOS occupies 0.072 mm2 and achieves a peak SNDR of 101 dB over 1 kHz bandwidth. It consumes 15.7 $\mu \text {W}$ from a 1.2 V supply at 1 MS/s and can be configured to Nyquist mode up to 5 MS/s. These features enable the application of SAR ADCs in high-precision, multi-purpose sensor readout interfaces.
Keywords
This publication has 18 references indexed in Scilit:
- An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOSIEEE Journal of Solid-State Circuits, 2016
- A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADCIEEE Journal of Solid-State Circuits, 2015
- An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic rangePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-StepIEEE Journal of Solid-State Circuits, 2013
- A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADCIEEE Journal of Solid-State Circuits, 2012
- Input-tracking DAC for low-power high-linearity SAR ADCElectronics Letters, 2011
- A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ProcedureIEEE Journal of Solid-State Circuits, 2010
- A self calibration technique for monolithic high-resolution D/A convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 15-b 1-Msample/s digitally self-calibrated pipeline ADCIEEE Journal of Solid-State Circuits, 1993
- A self-calibrating 15 bit CMOS A/D converterIEEE Journal of Solid-State Circuits, 1984