Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
- 31 March 2005
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 516-521
- https://doi.org/10.1109/isqed.2005.82
Abstract
Within-die spatial correlation of device parameter values caused by manufacturing variations [1] has a significant impact on circuit performance. Based on experimental and simulation results, we (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact on the variability of circuit performance.Keywords
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