High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder
Open Access
- 18 March 2010
- journal article
- research article
- Published by Springer Science and Business Media LLC in Nanoscale Research Letters
- Vol. 5 (5), 859-862
- https://doi.org/10.1007/s11671-010-9575-4
Abstract
Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.Keywords
This publication has 12 references indexed in Scilit:
- A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverterMicroelectronics Journal, 2009
- Two novel ultra high speed carbon nanotube Full-Adder cellsIEICE Electronics Express, 2009
- A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance BenchmarkingIEEE Transactions on Electron Devices, 2007
- CNTFET Modeling and Reconfigurable Logic-Circuit DesignIEEE Transactions on Circuits and Systems I: Regular Papers, 2007
- A Novel High-Speed and Energy Efficient 10-Transistor Full Adder DesignIEEE Transactions on Circuits and Systems I: Regular Papers, 2007
- Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic StyleIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
- Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic DesignIEEE Transactions on Nanotechnology, 2005
- Analysis and comparison on full adder block in submicron technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
- Low-power logic styles: CMOS versus pass-transistor logicIEEE Journal of Solid-State Circuits, 1997
- Low-power design techniques for high-performance CMOS addersIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995