An experimental chip to evaluate test techniques experiment results
Top Cited Papers
- 19 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 663-672
- https://doi.org/10.1109/test.1995.529895
Abstract
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.Keywords
This publication has 6 references indexed in Scilit:
- DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSISPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Very-low-voltage testing for weak CMOS logic ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new procedure for weighted random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An experimental chip to evaluate test techniques: chip and experiment designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A method for generating weighted random test patternsIBM Journal of Research and Development, 1989
- CrossCheck: a cell based VLSI testability solutionPublished by Association for Computing Machinery (ACM) ,1989