An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication

Abstract

We report results of an analysis of alignment data obtained from wafers aligned and oxide bonded in our facility. A description of an advanced wafer alignment tool currently under development is also presented. Two types of wafer pairs were measured for this work. Wafers from the first type, referred to as metal-only pairs, were fabricated by patterning a 630 nm thick Ti/AlSi/Ti/TiN metal layer that was deposited on thermally grown SiO/sub 2/ on bulk silicon substrates. The metal layer was then covered with PETEOS and LTO films and polished by CMP. No other lithographic layers were defined on these wafers. The other type, referred to as device pairs, consisted of single-metal photodiode wafers fabricated in bulk silicon and three-metal CMOS wafers fabricated using a 180 nm FDSOI process. All lithographic layers on all of the wafers were defined using a Canon FPA-3000 EX4 wafer stepper and a die-to-die spacing of 22 mm.