IRIS Feature Extraction and Classification using FPGA

Abstract

This paper proposes a new architecture for VLSI implementation of singular value decomposition for IRIS feature extraction and determining simple hamming distance for pattern classification. Using dedicated personal computers for such applications is economically not justified. The main aim of this work is to provide flexible and reprogrammable hardware solution based on field programmable gate array (FPGA) for feature extraction and classification. Keywords: Singular value decomposition, FPGA, Jacobi transformation, finite state machine.