3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
- 9 October 2018
- journal article
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 65 (11), 5165-5171
- https://doi.org/10.1109/ted.2018.2871265
Abstract
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 degrees C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 degrees C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V-G = V-th + 0.6 V, 125 degrees C), even without the use of "reliability" anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.Keywords
Funding Information
- 2018 Symposium on VLSI Technology, Honolulu, Hawaii
- IMEC
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