An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm
- 1 April 2007
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264/MPEG4 part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 90 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640times480) per secondKeywords
This publication has 2 references indexed in Scilit:
- Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coderIEEE Transactions on Circuits and Systems for Video Technology, 2005
- Rate-constrained coder control and comparison of video coding standardsIEEE Transactions on Circuits and Systems for Video Technology, 2003