Adaptive line placement with the set balancing cache
- 12 December 2009
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 529-540
- https://doi.org/10.1145/1669112.1669178
Abstract
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is the non-uniform distribution of the memory accesses on the cache sets. Its consequence is that while some cache sets may have working sets that are far from fitting in them, other sets may be underutilized because their working set has fewer lines than the set. In this paper we present a technique that aims to balance the pressure on the cache sets by detecting when it may be beneficial to associate sets, displacing lines from stressed sets to underutilized ones. This new technique, called Set Balancing Cache or SBC, achieved an average reduction of 13% in the miss rate of ten benchmarks from the SPEC CPU2006 suite, resulting in an average IPC improvement of 5%.Keywords
Funding Information
- Ministerio de Ciencia e Innovación (TIN2007-67536-C03-02)
This publication has 11 references indexed in Scilit:
- Adaptive insertion policies for high performance cachingPublished by Association for Computing Machinery (ACM) ,2007
- Balanced Cache: Reducing Conflict Misses of Direct-Mapped CachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- The V-Way Cache: Demand Based Associativity via Global ReplacementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Using Prime Numbers for Cache Indexing to Eliminate Conflict MissesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessorIEEE Journal of Solid-State Circuits, 2002
- A fully associative software-managed cache designACM SIGARCH Computer Architecture News, 2000
- Capturing dynamic memory reference behavior with adaptive cache topologyPublished by Association for Computing Machinery (ACM) ,1998
- Two fast and high-associativity cache schemesIEEE Micro, 1997
- Column-associative cachesPublished by Association for Computing Machinery (ACM) ,1993
- Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffersACM SIGARCH Computer Architecture News, 1990