Three-dimensional packaging for multi-chip module with through-the-silicon via hole

Abstract

This paper presents an innovative package design for multi-chip modules. The developed package has a flip-chip-on-chip structure. Four memory chips (DRAM for demonstration) are assembled on a silicon chip carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. An optional through-the-silicon via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of underfill. Afterwards, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of those packages is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1,000 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, right under the pads of large solder balls. The ATC test of packages with underfill encapsulation is still ongoing (no observable failure recorded up to 1,200 cycles). With this innovative package design, low profile and high density multi-chip modules can be implemented. Due to the unique package structure and underfill encapsulation, it is believed that good board level reliability can be achieved.