A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6 MB L2 cache of 461GB/S and the 308-pin SerDes I/O of 2.4 Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377 mm 2 die.