A Transaction Level Assertion Verification Framework in SystemC: An Application Study
- 1 October 2009
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2009 Second International Conference on Advances in Circuits, Electronics and Micro-electronics
Abstract
This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of assertion based verification in a model driven design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.Keywords
This publication has 6 references indexed in Scilit:
- System behaviour capture: from UML to SystemCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Implementation of a Transaction Level Assertion Framework in SystemCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Verification methodologies in a TLM-to-RTL design flowProceedings of the 39th conference on Design automation - DAC '02, 2007
- On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Model Driven Engineering for SoC co-designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Writing Testbenches: Functional Verification of HDL ModelsPublished by Springer Science and Business Media LLC ,2003