Model-based correction for local stress-induced overlay errors

Abstract

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers¹. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.