Optimum control design of PWM-buck topologies to minimize output impedance
- 25 June 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Optimizing the load transient response of the buck converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis and optimization of synchronous buck converter at high slew-rate load current transientsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuitsIEEE Transactions on Power Electronics, 1996