Analysis and synthesis of discrete event systems using temporal logic
- 9 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 140-145
- https://doi.org/10.1109/isic.1991.187347
Abstract
A systematic way of analyzing and synthesizing supervised discrete event systems using temporal logic is proposed. Syntax and semantics of temporal logic that are suitable for the study of supervised discrete-event systems are introduced. A systematic way is given to verify that a temporal logic formula is satisfied in a supervised discrete-event system. Given a temporal logic formula, a supervised discrete-event system satisfying the formula is synthesized. A synthesis algorithm is developed. The development is illustrated by examplesKeywords
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