Efficient Mapping of Addition Recurrence Algorithms in CMOS

Abstract

Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinbergerýs, Lingýs and Doranýs were analyzed for its flexibility in representation and suitability for realization in CMOS. We describe general techniques for developing efficient realizations based on CMOS technology constraints when using Lingýs algorithm. From these techniques we propose two high-performance realizations that achieve 1 FO4 delay improvement at the same energy and 50% energy reduction at the same delay than existing Ling and Weinberger designs.