Magic's Incremental Design-Rule Checker
- 1 January 1984
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 160-165
- https://doi.org/10.1109/dac.1984.1585790
Abstract
The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.Keywords
This publication has 3 references indexed in Scilit:
- Corner Stitching: A Data-Structuring Technique for VLSI Layout ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Magic: A VLSI Layout SystemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Lyra: A New Approach to Geometric Layout Rule CheckingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982