Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
- 19 August 2009
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- Statistical prediction of circuit aging under process variationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS TechnologyIEEE Transactions on Device and Materials Reliability, 2007
- Why we need statistical static timing analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Characterizing process variation in nanometer CMOSProceedings of the 39th conference on Design automation - DAC '02, 2007
- Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Predictive Modeling of the NBTI Effect for Reliable DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- NBTI degradation: From physical mechanisms to modellingMicroelectronics Reliability, 2006
- Statistical static timing analysisPublished by Association for Computing Machinery (ACM) ,2005
- Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulasIEEE Journal of Solid-State Circuits, 1990
- The Greatest of a Finite Set of Random VariablesOperations Research, 1961