Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer

Abstract

The metal–oxide–semiconductor (MOS)-based vertical tunnel field effect transistor (FET) on silicon has been proposed earlier and which showed gate-controlled band-to-band tunneling from the valence band in the heavily doped δp ⁺ layer at source to the conduction band in the inversion channel. In this work, using 2D computer simulation, we further investigate the device performance enhancement with SiGe in the δp ⁺ layer. On-current as well as threshold voltage are seen to improve considerably and meet the roadmap technology requirements. We also show that unlike the conventional MOSFET, the subthreshold swing of the vertical tunnel FET is not limited to the theoretical value of 60 mV/dec at room temperature.