On modelling and characterization of single electron transistor

Abstract

As the nanotechnology rose to the surface, single electron transistor (SET) was invented. In contrast to the well-known response of MOS current, SET current has peaks at certain gate voltages, which disappears at other gate voltages. The SET has promised to be valuable in many applications for its high speed and low power consumption. First, a comparison was drawn between different models of SET based on the orthodox theory. Such theory explains electron transport from source to drain, employing free energies, tunnel rates and coulomb blockade phenomenon, in addition to quantizing electron tunnelling. Afterwards, a simplified model was proposed to account for unnecessary lengthy calculation processes, resulting from the large number of states assumed for simulation. The proposed PSPICE simplified model was confirmed by comparing its results to the results of the available models, and it was found to agree well with them. Taking much less runtime than the available models, the proposed model can easily be used to simulate SET-based integrated circuits on PSPICE.