Modelling of breakdown voltage in sub-micron SOI transistors
- 4 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Characterization of negative resistance and bipolar latchup in thin film SOI transistors by two-dimensional numerical simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SIMOX and VLSI high speed and rad hard applications: discussion of floating body effects and circuits optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003