We present a method of automatic generation of iimc- tionsl vectors for sequential circuits. A high-level description of the circui~ in VHDL or C, is assumed available. Our method auto- matically transforms the high-level deacriptiorL in VHDL or C, of a circuit into an && jim"te state mochine (EFSM) model using which functional vectors are generated. The EFSM model is a gen- erslixation of the traditional state machine model. It can be consid- ered as a compact representation of h machine that preserves many nice properties of a traditional state machine. Theoretical background of the EFSM model will be addressed. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of cinnprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated sutmnsticslly in a few minutes of CPU time using our prototype system.