A channelless, multilayer router
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 25th ACM/IEEE, Design Automation Conference.Proceedings 1988.
- p. 667-671
- https://doi.org/10.1109/dac.1988.14839
Abstract
The authors have implemented a channelless, gridless, multilayer router as part of the Magic IC layout system. The router is designed to handle routing problems associated with emerging technologies such as wafer-scale integration and multilayered metal processes. Three features distinguish this router: rectilinear Steiner trees with floating segments a routing scheduler, and a corner-stitched database Author(s) Lunow, R.E. Lawrence Livermore Nat. Lab., CA, USAKeywords
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