This article presents our experience of designing double-row height standard cell libraries and their use for chip designs. Seven cell libraries are designed based on the 15nm process technology stipulated in FreePDK15. A single-row height of 7.5 M2 tracks is used as a basis for designing double-row height cells. Two minimum-sized transistors, one having two fins and the other having four fins, are employed to design 1X drive-strength cells. Among the seven libraries, two libraries consist of only single-row height cells. The other five libraries each consist of partly single-row height cells and double-row height cells. Our experiments show that a double-row height library can achieve on average -2% to 21% area saving and -23% to 19% smaller power-delay-area product. Our results also show that using a large minimum-sized transistor for designing a double-row height library is not viable if extensive transistor folding is required.

Obfuscation plays a key role in thwarting attacks launched through reverse engineering process. This work presents a new obfuscation process for DSP cores using improved logic locking and encryption that incurs minimum design overhead and achieves reduced design cost compared to state of the art approaches. The proposed approach integrates particle swarm optimization driven design space exploration system (PSO-DSE) for obtaining reduced design cost of obfuscated DSP designs. Enhanced security of locking is provided through locking blocks that are capable of locking each output data bit of functional resources with 8 key bits. The presented approach includes countermeasures against key sensitization attacks, SAT attacks and removal attacks. Results indicate that the proposed approach has been capable of achieving enhanced obfuscation security by at least 4.29 e+9 times and a design cost reduction ~ 6.5 % compared to a recent approach.

This paper introduces 375 nA input off current Schmitt trigger LDO, which is suitable for receiving the power from high internal impedance energy harvesting power sources. The Schmitt trigger LDO consumes 375nA input current at the input voltage of 0.5V, and occupies 276 × 295 um area using 0.18 um CMOS technology. The proposed Schmitt trigger LDO is used to make an Energy Harvesting Illumination Beat Sensor Node, so that the sensor node wirelessly transmits the data of illumination from 780 to 1540 lx without battery.

Convolutional neural networks (CNNs) have found extensive applications in practice. However, weight/activation's sparsity and different data precision requirements across layers lead to a large amount of redundant computations. In this paper, we propose an efficient architecture for CNNs, named Folded Precision-Adjustable Processor (FPAP), to skip those unnecessary computations with ease. Computations are folded in the following two aspects to achieve efficient computing. On one hand, the dominant multiply-and-add (MAC) operations are performed bit-serially based on a bit-pair encoding algorithm so that the FPAP can adapt to different numerical precisions without using multipliers with long data width. On the other hand, a 1-D convolution is undertaken by a multi-tap transposed finite impulse response (FIR) filter, which is folded into one tap so that computations involving zero activations and weights can be easily skipped. Equipped with the precision-adjustable MAC unit and the folded FIR filter structure, a well-designed array architecture, consisting of many identical processing elements is developed, which is scalable for different throughput requirements and highly flexible for different numerical precisions. Besides, a novel genetic algorithm based kernel reallocation scheme is introduced to mitigate the load imbalance issue. Our synthesis results demonstrate that the proposed FPAP can significantly reduce the logic complexity and the critical path over the corresponding unfolded design, which only delivers slightly higher throughput when processing sparse and compact models. Our experiments also show that FPAP can scale its energy efficiency from 1.01TOP/s/W to 6.26TOP/s/W under 90nm CMOS technology when different data precisions are used.

State-of-the-art system-on-chip (SoC) field programmable gate arrays (FPGAs) integrate hard powerful ARM processor cores and the reconfigurable logic fabric on a single chip in addition to many commonly needed high performance and high-bandwidth peripherals. The increasing reliance on untrustworthy third-party IP (3PIP) cores, including both hardware and software in FPGA-based embedded systems has made the latter increasingly vulnerable to security attacks. Detection of trojans in 3PIPs is extremely difficult to current static detection methods since there is no golden reference model for 3PIPs. Moreover, many FPGA-based embedded systems do not have the support of security services typically found in operating systems. In this paper, we present our run-time, low-cost, and low-latency hardware and software based solution for protecting data stored in on-chip memory blocks, which has attracted little research attention. The implemented memory protection design consists of a hierarchical top-down structure and controls memory access from software IPs running on the processor and hardware IPs running in the FPGA, based on a set of rules or access rights configurable at run time. Additionally, virtual addressing and encryption of data for each memory help protect confidentiality of data in case of a failure of the memory protection unit, making it hard for the attacker to gain access to the data stored in the memory. The design is implemented and tested on the Intel (Altera) DE1-SoC board featuring a SoC FPGA that integrates a dual-core ARM processor with reconfigurable logic and hundreds of memory blocks. The experimental results and case studies show that the protection model is successful in eliminating malicious IPs from the system without need for reconfiguration of the FPGA. It prevents unauthorized accesses from untrusted IPs, while arbitrating access from trusted IPs generating legal memory requests, without incurring a serious area or latency penalty.

In digitized world power efficient Successive Approximation Register Analog-to-Digital converter(SAR-ADC) architecture are widely used in most of the electronics applications. It is very compact compared to other ADC architecture. In this proposed paper practical implementation of modified 10-bit SARADC Clock Retiming is designed. The performance of the design is analyzed by Clock Retiming with multiple input phases and multiple output phases. As a result Electrical level of glitches is also removed by Retiming without altering the functionality of the design. The transient analysis of DAC output shows gain error reduction compared to earlier design proposed, after placing the delay element to each input line of the DAC circuit. The R-2R DAC architecture of SAR-ADC is designed using Sub-micron technology. As a result ADC topology shows the low power consumption with reduction in gain error.

Digital security practitioners are facing enormous challenge in face of the growing repertoire of physical attacks, e.g., Side Channel Attack (SCA) and Fault Injection Attack (FIA). Countermeasures to such threats are usually very different in nature and come with a significant performance penalty. While the FIA countermeasures rely on fault-detecting sensors or concurrent error detection schemes, SCA countermeasures are based on data masking or dual-rail logic circuits. Recently, a low-overhead FIA countermeasure has been proposed that utilises a ring oscillator circuit with Phase-Locked Loop (PLL). In this paper, we extend that countermeasure to further provide protection against SCA, thereby proposing PLL based Protection Against Physical attacks (PPAP). We demonstrate the PPAP on an FPGA prototype under rigorous SCA and FIA testing. We evaluate SCA resistance using the TVLA metric and observe a 2000× increase in SCA protection (in terms of number of traces) with PPAP. We further improve the security of PPAP using statistical analysis through an improved PPAP design (iPPAP) with an increase in SCA resistance of at least 5000× compared to the unprotected implementation with a minimal area overhead.

Ferroelectric FETs (FeFETs) are emerging as a promising nano device candidate for the next-generation energy-efficient embedded nonvolatile memory (NVM). This promise comes from not only the CMOS-scaling compatibility, but also the compact fusion of logic and non-volatility in a single device that provides opportunities for efficient memory access and in-memory computing. This talk investigates circuit opportunities that harness these intriguing FeFET device features, providing insights into new computation paradigms beyond existing solutions.

Intellectual property (IP) and integrated circuit (IC) piracy are of increasing concern to IP/IC providers because of the globalization of IC design flow and supply chains. Such globalization is driven by the cost associated with the design, fabrication, and testing of integrated circuits and allows avenues for piracy. To protect the designs against IC piracy, we propose a fingerprinting scheme based on side-channel power analysis and machine learning methods. The proposed method distinguishes the ICs which realize a modified netlist, yet same functionality. Our method doesn't imply any hardware overhead. We specifically focus on the ability to detect minimal design variations, as quantified by the number of logic gates changed. Accuracy of the proposed scheme is greater than 96 percent, and typically 99 percent in detecting one or more gate-level netlist changes. Additionally, the effect of temperature has been investigated as part of this work. Results depict 95.4 percent accuracy in detecting the exact number of gate changes when data and classifier use the same temperature, while training with different temperatures results in 33.6 percent accuracy. This shows the effectiveness of building temperature-dependent classifiers from simulations at known operating temperatures.

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